Rev |
Log message |
Author |
Age |
Path |
174 |
Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification. |
olivier.girard |
4148d 18h |
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v |
134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4462d 19h |
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v |
128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4559d 18h |
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v |
117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
4735d 20h |
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v |
111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4769d 19h |
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v |
105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4840d 18h |
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v |
103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4846d 01h |
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v |
102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4846d 18h |
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v |
34 |
To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. |
olivier.girard |
5276d 20h |
/openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v |
33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5276d 21h |
/openmsp430/trunk/core/rtl/verilog/execution_unit.v |
23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5397d 23h |
/openmsp430/trunk/core/rtl/verilog/execution_unit.v |
17 |
Updated header with SVN info |
olivier.girard |
5423d 18h |
/openmsp430/trunk/core/rtl/verilog/execution_unit.v |
2 |
Upload complete openMSP430 project to the SVN repository |
olivier.girard |
5458d 18h |
/openmsp430/trunk/core/rtl/verilog/execution_unit.v |