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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Rev 202

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Rev Log message Author Age Path
202 Add DMA interface support + LINT cleanup olivier.girard 3258d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3419d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
193 Update FPGA projects with latest core RTL changes. olivier.girard 3819d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4140d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4247d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
136 Update all FPGA projects with the latest core version. olivier.girard 4454d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4761d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4817d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4832d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4836d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4873d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4927d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v

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