OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] [version.texi] - Rev 784

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
784 Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.

2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour.		 jeremybennett 4445d 22h /openrisc/trunk/or1ksim/doc/version.texi
625 Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. jeremybennett 4665d 06h /openrisc/trunk/or1ksim/doc/version.texi
561 or1ksim - timer module, spr-defs.h re-bugfix julius 4729d 04h /openrisc/trunk/or1ksim/doc/version.texi
556 or1ksim - added performance counters unit and test for it. julius 4734d 22h /openrisc/trunk/or1ksim/doc/version.texi
552 or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets julius 4736d 07h /openrisc/trunk/or1ksim/doc/version.texi
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 4763d 03h /openrisc/trunk/or1ksim/doc/version.texi
510 Updates for release 0.5.1rc1. jeremybennett 4794d 06h /openrisc/trunk/or1ksim/doc/version.texi
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 4836d 23h /openrisc/trunk/or1ksim/doc/version.texi
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4887d 07h /openrisc/trunk/or1ksim/doc/version.texi
451 More tidying up. jeremybennett 4907d 22h /openrisc/trunk/or1ksim/doc/version.texi
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4908d 02h /openrisc/trunk/or1ksim/doc/version.texi
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4913d 20h /openrisc/trunk/or1ksim/doc/version.texi
440 Updated documentation to describe new Ethernet usage. jeremybennett 4914d 22h /openrisc/trunk/or1ksim/doc/version.texi
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4926d 23h /openrisc/trunk/or1ksim/doc/version.texi
432 Updates to handle interrupts correctly. jeremybennett 4928d 02h /openrisc/trunk/or1ksim/doc/version.texi
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 4930d 23h /openrisc/trunk/or1ksim/doc/version.texi
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 4933d 22h /openrisc/trunk/or1ksim/doc/version.texi
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 4942d 03h /openrisc/trunk/or1ksim/doc/version.texi
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 4942d 06h /openrisc/trunk/or1ksim/doc/version.texi
385 Updates for Or1ksim 0.5.0rc2.

* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.

* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected.		 jeremybennett 4982d 03h /openrisc/trunk/or1ksim/doc/version.texi

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.