URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [UartSC.cpp] - Rev 861

Rev	Log message	Author	Age	Path
861	sysc: include unistd.h write, read, pipe et al are declared in this, newer gcc will warn on missing declerations, thus making the build to fail	stekern	3990d 21h	/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp
500	ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc ML501 simulation makefile update to allow custom ELFs to be specified	julius	4836d 09h	/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	4898d 17h	/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5471d 08h	/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp
6	Checking in ORPSoCv2	julius	5494d 03h	/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp