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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [include/] [eth_stim.v] - Rev 439

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439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4933d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4961d 05h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4964d 19h /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5020d 02h /eth_stim.v
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5383d 00h /eth_stim.v
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5434d 10h /eth_stim.v

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