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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_alu.v] - Rev 803

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803 ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91		 julius 4379d 21h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
801 ORPSoC: Fix bug 88

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88		 julius 4385d 02h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
788 or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 julius 4443d 01h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
672 ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled

OR1200 RTL fix and software test added.		 julius 4545d 21h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
619 ORPSoC OR1200 fix and regression test for bug 51.

signed-off Julius Baxter
reviewed by Stefan Kristiansson		 julius 4677d 23h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
504 ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup julius 4819d 01h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default		 julius 4822d 01h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4823d 21h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4923d 20h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4952d 00h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5002d 12h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5004d 02h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
350 Adding new OR1200 processor to ORPSoCv2 julius 5007d 06h /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_alu.v

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