| Rev |
Log message |
Author |
Age |
Path |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
4952d 09h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4967d 13h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4969d 19h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 393 |
ORPSoCv2 software rearrangement in progress. Basic tests should now run again. |
julius |
4972d 18h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5018d 01h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5019d 10h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5019d 15h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5020d 09h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5021d 15h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5022d 15h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5022d 19h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 78 |
Fixed typo in Silos workaround script |
rherveille |
5175d 14h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5175d 14h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5223d 04h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5223d 05h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5225d 21h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5226d 00h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5245d 22h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5252d 23h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5262d 20h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
