URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit] - Rev 24

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Rev	Log message	Author	Age	Path
24	Added System Verilog Wishbone interface to module and testbench.	rehayes	4604d 08h	/pit
23	Simple language upgrade, will make bigger changes to add more system verilog features later.	rehayes	4689d 19h	/pit
22	Correct revision, compiles with VCS.	rehayes	4689d 19h	/pit
21	Simple language upgrade	rehayes	4690d 11h	/pit
20	minor update for timing constraint sugestions.	rehayes	5225d 13h	/pit
19	Minor change to add parameter to pit instance	rehayes	5225d 13h	/pit
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5225d 16h	/pit
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5239d 13h	/pit
16	Added master error counter variable, added simulation timout limit	rehayes	5350d 15h	/pit
15	Fix blocking assigment	rehayes	5378d 16h	/pit
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5447d 14h	/pit
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5477d 17h	/pit
12	Fixed for single cycle reads	rehayes	5478d 13h	/pit
11	Changed read task to capture data at rising edge of clock	rehayes	5478d 13h	/pit
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5479d 16h	/pit
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5485d 09h	/pit
8	Fix ack signal in testbench	rehayes	5485d 10h	/pit
7	Reflection of minor corrections	rehayes	5489d 15h	/pit
6	Reflection of minor corrections	rehayes	5489d 15h	/pit
5		rehayes	5527d 11h	/pit

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Subversion Repositories pit

[/] [pit] - Rev 24

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