URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk] - Rev 148

Rev	Log message	Author	Age	Path
148	New directory structure.	root	5571d 11h	/rise/trunk
147	- Updated to use current example.	cwalter	6345d 19h	/trunk
146	- Changed to compile UART example.	cwalter	6345d 21h	/trunk
145	- Added more VHDL files to project.	cwalter	6345d 21h	/trunk
144	- IF stage now uses autogenerated VHDL files.	cwalter	6345d 21h	/trunk
143	- Added more complex UART example.	cwalter	6345d 21h	/trunk
142	- Added gap between characters sent and changed last character to CR.	cwalter	6345d 22h	/trunk
141	- Added delay between characters.	cwalter	6345d 22h	/trunk
140	- Test bench for RISE with UART.	cwalter	6345d 22h	/trunk
139	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6345d 23h	/trunk
138	- Fixed binary to VHDL converter.	cwalter	6345d 23h	/trunk
137	- Added binary to VHDL converter.	cwalter	6345d 23h	/trunk
136	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6345d 23h	/trunk
135	uart_address_0 was a latch -> changed	ustadler	6346d 20h	/trunk
134	Added second test program for testing uart.	jlechner	6346d 20h	/trunk
133	- Fixed bug with ST opcodes.	cwalter	6346d 21h	/trunk
132	Added test program for testing uart.	jlechner	6346d 22h	/trunk
131	Changed high active resets to low active ones.	jlechner	6346d 22h	/trunk
130	Removed obsolete line	jlechner	6346d 22h	/trunk
129	Sample assembler program for accessing uart	jlechner	6346d 22h	/trunk