URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [RTF65002PIC.v] - Rev 30

Rev	Log message	Author	Age	Path
30	- added additional branches - modified the pc increment - modified interrupts, all vector through BRK - registered some decodes - added SUPPORT macros to allow core trimming	robfinch	3898d 11h	/rtf65002/trunk/rtl/verilog/RTF65002PIC.v
13	- fix overflow in immediate mode - fix bit instruction N,V setting - add vector base register, modified interrupt vectoring	robfinch	3916d 11h	/rtf65002/trunk/rtl/verilog/RTF65002PIC.v
10	- fix rind mode in 32 bit mode - fix flag update in 32 bit mode for RR instructions - initialize cache tags - added flag to disable ints until after sp load	robfinch	3919d 16h	/rtf65002/trunk/rtl/verilog/RTF65002PIC.v