URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [calc.v] - Rev 30

Rev	Log message	Author	Age	Path
30	- added additional branches - modified the pc increment - modified interrupts, all vector through BRK - registered some decodes - added SUPPORT macros to allow core trimming	robfinch	3907d 14h	/rtf65002/trunk/rtl/verilog/calc.v
21	- config processor mode on reset - D flag flags extended precision for add/sub - added software interrupt call facility - unimplmented opcode vectoring - bus error signal support - merge load states to reduce core size - zero out ir during interrupt	robfinch	3922d 09h	/rtf65002/trunk/rtl/verilog/calc.v
20	- greater separation of emulation and native mode in source code - fix instruction buffer fetch for non-cached accesses - fix the sta (d),y instruction	robfinch	3923d 15h	/rtf65002/trunk/rtl/verilog/calc.v
19	- added multibit shifts - added eight bit CMP instruction	robfinch	3924d 14h	/rtf65002/trunk/rtl/verilog/calc.v
13	- fix overflow in immediate mode - fix bit instruction N,V setting - add vector base register, modified interrupt vectoring	robfinch	3925d 14h	/rtf65002/trunk/rtl/verilog/calc.v
10	- fix rind mode in 32 bit mode - fix flag update in 32 bit mode for RR instructions - initialize cache tags - added flag to disable ints until after sp load	robfinch	3928d 19h	/rtf65002/trunk/rtl/verilog/calc.v
5	setting up project	robfinch	3932d 02h	/rtf65002/trunk/rtl/verilog/calc.v