URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [grpSd/] [pkgSd/] [src/] [Sd-p.vhdl] - Rev 185

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Rev	Log message	Author	Age	Path
185	Restructuring as source repository: Moved sources out of src subdirectory.	rkastl	4893d 14h	/sdhc-sc-core/trunk/grpSd/pkgSd/src/Sd-p.vhdl
170	License rewritten to BSD	rkastl	4896d 08h	/Sd-p.vhdl
164	Headers updated (LGPL, consistent format)	rkastl	4896d 08h	/Sd-p.vhdl
157	Verification: Testcase with Reads works but Verification not completly implemented.	rkastl	4896d 08h	/Sd-p.vhdl
134	SdData: Further refactoring.	rkastl	4896d 08h	/Sd-p.vhdl
133	SdData: Further refactoring	rkastl	4896d 08h	/Sd-p.vhdl
132	SdData: Refactoring, not done. Testbench works again, but does not really test anything.	rkastl	4896d 08h	/Sd-p.vhdl
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	4896d 08h	/Sd-p.vhdl
123	Write: Must be able to halt SdClk, rest is done.	rkastl	4896d 08h	/Sd-p.vhdl
113	Read with single block works on cards, but not in simulation. SdData.sv sends data with one "XXXX" cycle right before the crc.	rkastl	4896d 12h	/Sd-p.vhdl
111	Sclk moved to neg. edge -> setup and hold times for fast mode are easier to reach. (only micro sd does not work in fast mode).	rkastl	4896d 12h	/Sd-p.vhdl
109	Added a data ram.	rkastl	4896d 12h	/Sd-p.vhdl
104	SdController: Configuration ready to switch to high speed, refs #33	rkastl	4896d 12h	/Sd-p.vhdl
103	SdController: Checking speed works	rkastl	4896d 12h	/Sd-p.vhdl
102	SdController: Enabling wide mode works, refs #33	rkastl	4896d 12h	/Sd-p.vhdl
101	Receiving response to ACMD51 works including data, refs #33.	rkastl	4896d 12h	/Sd-p.vhdl
100	SdController: Receiving data after ACMD51, but CRC is wrong	rkastl	4896d 12h	/Sd-p.vhdl
99	SdController: Checking bus width without receiving data response	rkastl	4896d 12h	/Sd-p.vhdl
98	SdController: Receive response to CMD7 (except when busy is activated)	rkastl	4896d 12h	/Sd-p.vhdl
95	SdController: entity and architecture split, all outputs registered SdCardModel: Delay between response and next command added SdData: Busy checking refs #33	rkastl	4896d 12h	/Sd-p.vhdl

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Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [grpSd/] [pkgSd/] [src/] [Sd-p.vhdl] - Rev 185

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