URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [grpSd/] [unitSdClockMaster/] [src/] [SdClockMaster-Rtl-a.vhdl] - Rev 185

Rev	Log message	Author	Age	Path
185	Restructuring as source repository: Moved sources out of src subdirectory.	rkastl	4898d 18h	/sdhc-sc-core/trunk/grpSd/unitSdClockMaster/src/SdClockMaster-Rtl-a.vhdl
170	License rewritten to BSD	rkastl	4901d 12h	/SdClockMaster-Rtl-a.vhdl
164	Headers updated (LGPL, consistent format)	rkastl	4901d 12h	/SdClockMaster-Rtl-a.vhdl
152	SdClockMaster: Generate InStrobe so that it the sd bus gets captured on the rising edge of the clock in high speed mode	rkastl	4901d 12h	/SdClockMaster-Rtl-a.vhdl
150	Testbed: + Simulation made possible + Write works - Sometimes the alignment in the block is not right	rkastl	4901d 12h	/SdClockMaster-Rtl-a.vhdl
146	SdClockMaster: + fixed output of data at negedge of sclk in high speed mode	rkastl	4901d 12h	/SdClockMaster-Rtl-a.vhdl
130	SdClockMaster: Formal verification	rkastl	4901d 12h	/SdClockMaster-Rtl-a.vhdl
129	SdClockMaster: Redesigned, not finished. Tb with PSL assertions.	rkastl	4901d 12h	/SdClockMaster-Rtl-a.vhdl
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	4901d 12h	/SdClockMaster-Rtl-a.vhdl
125	Write works in simulation	rkastl	4901d 12h	/SdClockMaster-Rtl-a.vhdl
124	Write: SdClk is disabled, if no data is available.	rkastl	4901d 12h	/SdClockMaster-Rtl-a.vhdl
121	SdWbSlave inserted into SdTop. SdController does not use it yet.	rkastl	4901d 16h	/SdClockMaster-Rtl-a.vhdl