URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [grpSd/] [unitSdData/] [src/] [SdData-e.vhdl] - Rev 185

Rev	Log message	Author	Age	Path
185	Restructuring as source repository: Moved sources out of src subdirectory.	rkastl	4893d 15h	/sdhc-sc-core/trunk/grpSd/unitSdData/src/SdData-e.vhdl
170	License rewritten to BSD	rkastl	4896d 09h	/SdData-e.vhdl
165	Only use synchronous high active reset in SDHC-SC-Core.	rkastl	4896d 09h	/SdData-e.vhdl
164	Headers updated (LGPL, consistent format)	rkastl	4896d 09h	/SdData-e.vhdl
132	SdData: Refactoring, not done. Testbench works again, but does not really test anything.	rkastl	4896d 09h	/SdData-e.vhdl
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	4896d 09h	/SdData-e.vhdl
124	Write: SdClk is disabled, if no data is available.	rkastl	4896d 09h	/SdData-e.vhdl
123	Write: Must be able to halt SdClk, rest is done.	rkastl	4896d 09h	/SdData-e.vhdl
111	Sclk moved to neg. edge -> setup and hold times for fast mode are easier to reach. (only micro sd does not work in fast mode).	rkastl	4896d 13h	/SdData-e.vhdl
109	Added a data ram.	rkastl	4896d 13h	/SdData-e.vhdl
105	Changing speed works! refs #33	rkastl	4896d 13h	/SdData-e.vhdl
101	Receiving response to ACMD51 works including data, refs #33.	rkastl	4896d 13h	/SdData-e.vhdl
92	SdData: Sending in standard and wide mode (incl. simple not automated testbench and synthesis), refs #31.	rkastl	4896d 13h	/SdData-e.vhdl