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[/] [sdhc-sc-core/] [trunk/] [grpSdVerification/] [unitSdVerificationTestbench/] [src/] [SdVerificationTestbench.sv] - Rev 185

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185 Restructuring as source repository: Moved sources out of src subdirectory. rkastl 4893d 14h /sdhc-sc-core/trunk/grpSdVerification/unitSdVerificationTestbench/src/SdVerificationTestbench.sv
184 Removed WbSlave shell (refs #69)
Moved verification sources to grpSdVerification (fixes #70)		 rkastl 4896d 07h /SdVerificationTestbench.sv
170 License rewritten to BSD rkastl 4896d 08h /SdVerificationTestbench.sv
165 Only use synchronous high active reset in SDHC-SC-Core. rkastl 4896d 08h /SdVerificationTestbench.sv
164 Headers updated (LGPL, consistent format) rkastl 4896d 08h /SdVerificationTestbench.sv
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4896d 08h /SdVerificationTestbench.sv
157 Verification:
Testcase with Reads works but Verification not completly
implemented.		 rkastl 4896d 08h /SdVerificationTestbench.sv
156 SdVerification:
+ Split a SdCoreTransaction into multiple WbTransactions: Proof
of Concept with a ReadSingleBlock-Transaction
+ Finish after certain amount of time and present simulation
result		 rkastl 4896d 08h /SdVerificationTestbench.sv
153 SdVerification:
further development, not done by far		 rkastl 4896d 08h /SdVerificationTestbench.sv
151 Verification:
+ redesign: not functional yet		 rkastl 4896d 08h /SdVerificationTestbench.sv
148 SdVerification:
+ CardModel: Execution thread which starts initialization and
then receives token and parses them.

TbdSd:
+ Added SdWbSdSynchronization.		 rkastl 4896d 08h /SdVerificationTestbench.sv
145 Verification:
+ SdCardModel and SdBFM seperated		 rkastl 4896d 08h /SdVerificationTestbench.sv
135 Multiple-Inclusion-Protection to SystemVerilog files added
Stops using relative paths in `includes. instead +incdir has to be used.		 rkastl 4896d 08h /SdVerificationTestbench.sv
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4896d 08h /SdVerificationTestbench.sv
125 Write works in simulation rkastl 4896d 08h /SdVerificationTestbench.sv
124 Write: SdClk is disabled, if no data is available. rkastl 4896d 08h /SdVerificationTestbench.sv
123 Write: Must be able to halt SdClk, rest is done. rkastl 4896d 08h /SdVerificationTestbench.sv
122 SdController: Initial read support rkastl 4896d 12h /SdVerificationTestbench.sv
111 Sclk moved to neg. edge -> setup and hold times for fast mode are easier
to reach. (only micro sd does not work in fast mode).		 rkastl 4896d 12h /SdVerificationTestbench.sv
105 Changing speed works! refs #33 rkastl 4896d 12h /SdVerificationTestbench.sv

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