URL https://opencores.org/ocsvn/sha256_hash_core/sha256_hash_core/trunk

Subversion Repositories sha256_hash_core

[/] [sha256_hash_core/] [trunk/] [syn/] [sha256/] [iseconfig/] [gv_sha256.xreport] - Rev 8

Rev	Log message	Author	Age	Path
8	Streamlined VHDL code to eliminate wire and combinational "initialization", changed all 'X' to 'U' on input signals, consisted comments.	jdoin	2872d 13h	/sha256_hash_core/trunk/syn/sha256/iseconfig/gv_sha256.xreport
7	Delete intermediate files from repository. All commits are done after a Project/Cleanup.	jdoin	2874d 23h	/sha256_hash_core/trunk/syn/sha256/iseconfig/gv_sha256.xreport
6	Added Sim_test_1.png and Sim_test_8.png simulation pictures. Changed testbench for faster data input. Changed License text on all files. Consolidated file header info.	jdoin	2874d 23h	/sha256_hash_core/trunk/syn/sha256/iseconfig/gv_sha256.xreport
3	Added GV_SHA256 block logic schematics.	jdoin	2876d 05h	/sha256_hash_core/trunk/syn/sha256/iseconfig/gv_sha256.xreport
2	SHA256 RTL code simulated and verified, to all NIST verification vectors. Pre-par synthesis show 74MHz clock rate, with no pipelining.	jdoin	2876d 07h	/sha256_hash_core/trunk/syn/sha256/iseconfig/gv_sha256.xreport