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[/] [socgen/] [trunk/] [Makefile] - Rev 133

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133 Added Desing databases and foundation for elaborations tools jt_eaton 3323d 07h /socgen/trunk/Makefile
131 Added elaboration databases and tools
Added bus map creation tools		 jt_eaton 3355d 04h /socgen/trunk/Makefile
130 Dec 2014 major release
trimmed out some IP
replaced perl database with Berkeley		 jt_eaton 3458d 21h /socgen/trunk/Makefile
128 major cleanup
added toolflows for sim,syn,documentation,linting and verilog
added documentation tools		 jt_eaton 3914d 04h /socgen/trunk/Makefile
127 final cleanup before DAC jt_eaton 4029d 00h /socgen/trunk/Makefile
126 added mor1kx
cleanup		 jt_eaton 4082d 05h /socgen/trunk/Makefile
125 Added two new 6502 cores in www.6502.org

cleaned up sogen xml files and added module name control		 jt_eaton 4126d 23h /socgen/trunk/Makefile
121 cleaned up sims, added autogenerated test bench files
removed mrisc and experimental or1k code		 jt_eaton 4223d 03h /socgen/trunk/Makefile
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace		 jt_eaton 4275d 21h /socgen/trunk/Makefile
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs		 jt_eaton 4311d 07h /socgen/trunk/Makefile
117 added yellow pages tools jt_eaton 4339d 02h /socgen/trunk/Makefile
113 started refactoring or1200 jt_eaton 4435d 19h /socgen/trunk/Makefile
112 added more test sims
removed unneeded files		 jt_eaton 4445d 08h /socgen/trunk/Makefile
106 checked in orp_soc project step 2 jt_eaton 4469d 02h /socgen/trunk/Makefile
103 added user guide
resynced to local repository		 jt_eaton 4493d 23h /socgen/trunk/Makefile
102 all ip-xact files now readable by kactus2 jt_eaton 4555d 18h /socgen/trunk/Makefile
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT		 jt_eaton 4556d 20h /socgen/trunk/Makefile
100 created workspace prroject=fpga_mrisc for single compile
general cleanup		 jt_eaton 4569d 04h /socgen/trunk/Makefile
99 moved all projects into /projects/opencores.org
added build_register
added fizzim		 jt_eaton 4611d 20h /socgen/trunk/Makefile
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims		 jt_eaton 4648d 02h /socgen/trunk/Makefile

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