URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [sys/] [build_generate] - Rev 128

Rev	Log message	Author	Age	Path
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3912d 18h	/socgen/trunk/tools/sys/build_generate
127	final cleanup before DAC	jt_eaton	4027d 15h	/socgen/trunk/tools/sys/build_generate
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4274d 12h	/socgen/trunk/tools/sys/build_generate
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4309d 22h	/socgen/trunk/tools/sys/build_generate
117	added yellow pages tools	jt_eaton	4337d 16h	/socgen/trunk/tools/sys/build_generate