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[/] [socgen/] [trunk/] [tools/] [sys/] [soc_link_child] - Rev 127

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Rev Log message Author Age Path
127 final cleanup before DAC jt_eaton 4033d 15h /socgen/trunk/tools/sys/soc_link_child
125 Added two new 6502 cores in www.6502.org

cleaned up sogen xml files and added module name control
jt_eaton 4131d 14h /socgen/trunk/tools/sys/soc_link_child
124 beta release candidate 1
changed design.xml name
aligned schema with filesystem
jt_eaton 4184d 17h /socgen/trunk/tools/sys/soc_link_child
121 cleaned up sims, added autogenerated test bench files
removed mrisc and experimental or1k code
jt_eaton 4227d 18h /socgen/trunk/tools/sys/soc_link_child
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench
jt_eaton 4245d 18h /socgen/trunk/tools/sys/soc_link_child
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace
jt_eaton 4280d 12h /socgen/trunk/tools/sys/soc_link_child
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs
jt_eaton 4315d 22h /socgen/trunk/tools/sys/soc_link_child
117 added yellow pages tools jt_eaton 4343d 16h /socgen/trunk/tools/sys/soc_link_child
115 split or1200_cpu up into all ip-xact components
removed dead files
jt_eaton 4422d 18h /socgen/trunk/tools/sys/soc_link_child
107 added designCfg files to all modules jt_eaton 4468d 00h /socgen/trunk/tools/sys/soc_link_child
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT
jt_eaton 4561d 11h /socgen/trunk/tools/sys/soc_link_child
99 moved all projects into /projects/opencores.org
added build_register
added fizzim
jt_eaton 4616d 11h /socgen/trunk/tools/sys/soc_link_child
94 socgen now supports both sim and syn views
now allow each xml file to set its destination
jt_eaton 4762d 12h /socgen/trunk/tools/sys/soc_link_child

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