URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [verilog/] [gen_verilogLib] - Rev 131

Rev	Log message	Author	Age	Path
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3359d 21h	/socgen/trunk/tools/verilog/gen_verilogLib
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3463d 14h	/socgen/trunk/tools/verilog/gen_verilogLib
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3918d 20h	/socgen/trunk/tools/verilog/gen_verilogLib
127	final cleanup before DAC	jt_eaton	4033d 16h	/socgen/trunk/tools/verilog/gen_verilogLib
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4245d 20h	/socgen/trunk/tools/verilog/gen_verilogLib
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4280d 14h	/socgen/trunk/tools/verilog/gen_verilogLib