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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Rev 246

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246 Added some older files plus the first syn script creep 5450d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
146 Fixed ticket #13: reset behavior in the FSM. creep 5547d 01h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
117 Fixed the top level and connected the entire project. creep 5554d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
116 Changed the module instantiation into the dot form. creep 5554d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
115 Renamed the signal control. It is mem_rw now. creep 5554d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
112 Created a global timescale file for the project. creep 5554d 09h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
111 Performed some linting after coding was finished. creep 5555d 00h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5555d 01h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
109 PLA and PLP are coded and simulated. creep 5555d 04h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
108 PHA and PHP are coded and simulated. creep 5555d 05h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
107 The RTS instruction is working fine. Coded and simulated. creep 5555d 06h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
105 The RTI instruction is working fine. Coded and simulated. creep 5555d 06h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
104 The BRK instruction is working. The reset vector was tested also. creep 5555d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
102 Some early modifications to support the special stack instructions. creep 5556d 04h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
101 Absolute indirect addressing mode is coded and simulated. creep 5556d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
100 IDY WRITE TYPE instructions are coded and simulated. creep 5556d 09h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
98 Updated status and some comments. creep 5556d 09h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 5559d 01h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
95 IDX addressing mode is also 100%, coded and simulated. creep 5559d 05h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 5560d 01h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v

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