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[/] [tv80/] [trunk] - Rev 84

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Rev Log message Author Age Path
84 New directory structure. root 5565d 15h /tv80/trunk
83 Some fixes from Guy-- replace case with casex. hharte 5638d 21h /trunk
82 Clean up spacing hharte 5648d 17h /trunk
81 Initial version of TV80 Wishbone Wrapper hharte 5648d 18h /trunk
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.
ghutchis 6748d 06h /trunk
79 Added JR self-checking test ghutchis 6748d 06h /trunk
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6791d 07h /trunk
77 Added back files lost after server crash ghutchis 6823d 01h /trunk
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.
ghutchis 6902d 07h /trunk
74 Changed default for T2Write to be 1, to match expected behavior for
most users.
ghutchis 6902d 08h /trunk
73 Added RC4 encrypt/decrypt test ghutchis 6914d 03h /trunk
72 Added copyright header ghutchis 6914d 03h /trunk
71 Ported UART from T80 ghutchis 6975d 07h /trunk
70 Added test for T16450 UART ghutchis 7026d 02h /trunk
69 Added UART instance in testbench, and added UART to compile list. ghutchis 7026d 02h /trunk
68 Updated nwtest to reflect changes in register interface to simple_gmii.
In particular, interrupt bits for packet arrival and sending now need
to be explicitly cleared afterwards.
ghutchis 7034d 03h /trunk
67 Updated register generator based on testing with simple_gmii. Changed
how interrupt output mux is created, fixed many bugs.
ghutchis 7034d 03h /trunk
66 Modified top level testbench to reflect changes in simple_gmii block ghutchis 7034d 03h /trunk
65 Major restructuring of simple_gmii block.

1) Changed simple_gmii block to simple_gmii_core
2) Migrated RAM instances out of core into top level
3) Removed CPU interface logic and created CPU interface block using
register generator
4) Changed status register to interrupt register and added interrupt
logic
ghutchis 7034d 03h /trunk
64 Created rgen script and expanded available register types ghutchis 7035d 01h /trunk

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