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[/] [uart16550/] [tags/] [rel_2/] - Rev 106

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106 New directory structure. root 5563d 16h /uart16550/tags/rel_2
97 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7372d 22h /tags/rel_2
96 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish. tadejm 7372d 22h /trunk
95 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish. tadejm 7372d 22h /trunk
94 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7372d 22h /trunk
93 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7372d 22h /trunk
92 This is revision 1.4, revision 1.5 was put there by mistake. simons 7486d 15h /trunk
91 Removed files due to new complete testbench. tadejm 7487d 06h /trunk
90 Add Flextronics header avisha 7489d 13h /trunk
89 adjusted comment + define dries 7569d 18h /trunk
88 added clearing the receiver fifo statuses on resets gorban 7632d 08h /trunk
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7662d 09h /trunk
86 restored include for uart_defines.v in uart_test.v gorban 7932d 13h /trunk
85 Updated documentation to include latest changes. gorban 7966d 05h /trunk
84 The uart_defines.v file is included again in sources. gorban 7979d 05h /trunk
83 Reverted to include uart_defines.v file in other files again. gorban 7979d 05h /trunk
82 Updated to work with latest core. gorban 7986d 03h /trunk
81 Added lastest additions. gorban 7986d 03h /trunk
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 7986d 03h /trunk
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7986d 03h /trunk

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