URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_defines.v] - Rev 45

Rev	Log message	Author	Age	Path
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8223d 07h	/uart16550/trunk/rtl/verilog/uart_defines.v
29	Things connected to parity changed. Clock devider changed.	mohor	8317d 08h	/uart16550/trunk/rtl/verilog/uart_defines.v
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8318d 13h	/uart16550/trunk/rtl/verilog/uart_defines.v