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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_regs.v] - Rev 79

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79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7985d 02h /uart16550/trunk/rtl/verilog/uart_regs.v
68 lsr[7] was not showing overrun errors. mohor 8192d 12h /uart16550/trunk/rtl/verilog/uart_regs.v
66 rx push changed to be only one cycle wide. mohor 8199d 12h /uart16550/trunk/rtl/verilog/uart_regs.v
64 Warnings cleared. mohor 8200d 17h /uart16550/trunk/rtl/verilog/uart_regs.v
63 Synplicity was having troubles with the comment. mohor 8200d 17h /uart16550/trunk/rtl/verilog/uart_regs.v
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8202d 15h /uart16550/trunk/rtl/verilog/uart_regs.v
59 MSR register fixed. mohor 8205d 12h /uart16550/trunk/rtl/verilog/uart_regs.v
58 After reset modem status register MSR should be reset. mohor 8205d 15h /uart16550/trunk/rtl/verilog/uart_regs.v
56 thre irq should be cleared only when being source of interrupt. mohor 8206d 15h /uart16550/trunk/rtl/verilog/uart_regs.v
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8207d 16h /uart16550/trunk/rtl/verilog/uart_regs.v
52 Scratch register added gorban 8209d 05h /uart16550/trunk/rtl/verilog/uart_regs.v
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8213d 10h /uart16550/trunk/rtl/verilog/uart_regs.v
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8216d 03h /uart16550/trunk/rtl/verilog/uart_regs.v
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8221d 05h /uart16550/trunk/rtl/verilog/uart_regs.v
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8223d 03h /uart16550/trunk/rtl/verilog/uart_regs.v
44 fixed more typo bugs gorban 8237d 03h /uart16550/trunk/rtl/verilog/uart_regs.v
43 lsr1r error fixed. mohor 8237d 10h /uart16550/trunk/rtl/verilog/uart_regs.v
42 ti_int_pnd error fixed. mohor 8237d 10h /uart16550/trunk/rtl/verilog/uart_regs.v
41 ti_int_d error fixed. mohor 8237d 10h /uart16550/trunk/rtl/verilog/uart_regs.v
40 Synthesis bugs fixed. Some other minor changes gorban 8239d 12h /uart16550/trunk/rtl/verilog/uart_regs.v

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