URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_top.v] - Rev 65

Rev	Log message	Author	Age	Path
65	Warnings fixed (unused signals removed).	mohor	8208d 02h	/uart16550/trunk/rtl/verilog/uart_top.v
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8220d 20h	/uart16550/trunk/rtl/verilog/uart_top.v
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8223d 13h	/uart16550/trunk/rtl/verilog/uart_top.v
37	Heavily rewritten interrupt and LSR subsystems. Many bugs hopefully squashed.	gorban	8249d 17h	/uart16550/trunk/rtl/verilog/uart_top.v
33	Small synopsis fixes	gorban	8268d 01h	/uart16550/trunk/rtl/verilog/uart_top.v
30	Modified port names again	gorban	8323d 19h	/uart16550/trunk/rtl/verilog/uart_top.v
29	Things connected to parity changed. Clock devider changed.	mohor	8324d 13h	/uart16550/trunk/rtl/verilog/uart_top.v
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8325d 18h	/uart16550/trunk/rtl/verilog/uart_top.v