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Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_transmitter.v] - Rev 48

Rev	Log message	Author	Age	Path
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8224d 01h	/uart16550/trunk/rtl/verilog/uart_transmitter.v
39	Comments in Slovene language deleted, few small fixes for better work of old tools. IRQs need to be fix.	mohor	8249d 07h	/uart16550/trunk/rtl/verilog/uart_transmitter.v
37	Heavily rewritten interrupt and LSR subsystems. Many bugs hopefully squashed.	gorban	8250d 04h	/uart16550/trunk/rtl/verilog/uart_transmitter.v
34	fixed parity sending and tx_fifo resets over- and underrun	gorban	8259d 05h	/uart16550/trunk/rtl/verilog/uart_transmitter.v
33	Small synopsis fixes	gorban	8268d 12h	/uart16550/trunk/rtl/verilog/uart_transmitter.v
29	Things connected to parity changed. Clock devider changed.	mohor	8325d 01h	/uart16550/trunk/rtl/verilog/uart_transmitter.v
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8326d 06h	/uart16550/trunk/rtl/verilog/uart_transmitter.v