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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_transmitter.v] - Rev 74

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74 tf_overrun signal was disabled since it was not used gorban 8143d 15h /uart16550/trunk/rtl/verilog/uart_transmitter.v
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8180d 19h /uart16550/trunk/rtl/verilog/uart_transmitter.v
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8202d 15h /uart16550/trunk/rtl/verilog/uart_transmitter.v
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8216d 08h /uart16550/trunk/rtl/verilog/uart_transmitter.v
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8241d 15h /uart16550/trunk/rtl/verilog/uart_transmitter.v
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8242d 12h /uart16550/trunk/rtl/verilog/uart_transmitter.v
34 fixed parity sending and tx_fifo resets over- and underrun gorban 8251d 13h /uart16550/trunk/rtl/verilog/uart_transmitter.v
33 Small synopsis fixes gorban 8260d 20h /uart16550/trunk/rtl/verilog/uart_transmitter.v
29 Things connected to parity changed.
Clock devider changed.		 mohor 8317d 09h /uart16550/trunk/rtl/verilog/uart_transmitter.v
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8318d 14h /uart16550/trunk/rtl/verilog/uart_transmitter.v

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