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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_transmitter.v] - Rev 79

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79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7993d 04h /uart16550/trunk/rtl/verilog/uart_transmitter.v
74 tf_overrun signal was disabled since it was not used gorban 8151d 11h /uart16550/trunk/rtl/verilog/uart_transmitter.v
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8188d 15h /uart16550/trunk/rtl/verilog/uart_transmitter.v
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8210d 12h /uart16550/trunk/rtl/verilog/uart_transmitter.v
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8224d 05h /uart16550/trunk/rtl/verilog/uart_transmitter.v
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8249d 12h /uart16550/trunk/rtl/verilog/uart_transmitter.v
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8250d 09h /uart16550/trunk/rtl/verilog/uart_transmitter.v
34 fixed parity sending and tx_fifo resets over- and underrun gorban 8259d 10h /uart16550/trunk/rtl/verilog/uart_transmitter.v
33 Small synopsis fixes gorban 8268d 17h /uart16550/trunk/rtl/verilog/uart_transmitter.v
29 Things connected to parity changed.
Clock devider changed.		 mohor 8325d 06h /uart16550/trunk/rtl/verilog/uart_transmitter.v
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8326d 11h /uart16550/trunk/rtl/verilog/uart_transmitter.v

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