OpenCores
URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_wb.v] - Rev 29

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
29 Things connected to parity changed.
Clock devider changed.		 mohor 8317d 10h /uart16550/trunk/rtl/verilog/uart_wb.v
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8318d 15h /uart16550/trunk/rtl/verilog/uart_wb.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.