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[/] [usbhostslave/] [trunk/] [RTL/] [serialInterfaceEngine/] [processRxBit.v] - Rev 44

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Rev Log message Author Age Path
44 usbhostslave Version 2.2 - Fixed bugs in low speed communications via hub. Increased delay from data in to ACK. Fixed low speed ACK SOF collision bug sfielding 4831d 22h /usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
40 New directory structure. root 5570d 05h /usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
37 usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project sfielding 5767d 15h /usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
34 *** empty log message *** sfielding 6446d 09h /usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
22 Release 1.2 sfielding 6448d 11h /usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
14 Added LS keep alive, fixed clock recovery bug sfielding 7032d 11h /usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
12 try again sfielding 7063d 02h /usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
9 Fixed bus turn-around problems, added version number sfielding 7080d 02h /usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
7 Fixed some blocking assignments, changed module name, fixed SOF_TX_TIME sfielding 7100d 01h /usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
5 Removed html documentation sfielding 7113d 01h /usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
2 Created sfielding 7181d 11h /usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v

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