URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram_dc_dw.v] - Rev 26

Rev	Log message	Author	Age	Path
26	added ACTEL synthesis directive as define, +ACTEL	unneback	5038d 16h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
18	ADDR and DATA width set to 8 resp 32	unneback	5197d 16h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
17	based on updated versatile counter	unneback	5201d 14h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
15	doc updated gray_counter_defines added dual port RAM updated	unneback	5468d 18h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
12	no mux on dual port mem read	unneback	5526d 19h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
8		unneback	5532d 19h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
7		unneback	5532d 19h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
4		unneback	5533d 02h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v