URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

[/] [wb2axip/] [trunk/] [rtl] - Rev 12

Rev	Log message	Author	Age	Path
12	Added Verilators obj_dir to the list of ignored files	dgisselq	2367d 14h	/wb2axip/trunk/rtl
8	The WB to AXI translator wrks and works well. A proof of this will be added shortly.	dgisselq	2367d 15h	/wb2axip/trunk/rtl
7	Simplified.	dgisselq	2684d 15h	/wb2axip/trunk/rtl
6	IT WORKS!!! (On non-pipelined data--havent tested it on pipelined stuff .. yet)	dgisselq	2812d 10h	/wb2axip/trunk/rtl
5	Adjusted variable names to match the spec and the MIG.	dgisselq	2817d 01h	/wb2axip/trunk/rtl
4	Adjusted the core quickly so it should work for 128-bit wide wishbone busses as well as 32-bit wide busses.	dgisselq	2817d 07h	/wb2axip/trunk/rtl
3	Fixed the Verilator compile-time bugs. Still haven't tested the core.	dgisselq	2817d 07h	/wb2axip/trunk/rtl
2	Initial check in. Core not (yet) tested, verified, or validated.	dgisselq	2817d 08h	/wb2axip/trunk/rtl