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[/] [wbddr3/] [trunk/] [rtl/] [wbddrsdram.v] - Rev 14

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14 Lots of changes. Redesigned the refresh logic, and the activate/precharge
logic. While it's still not working on the hardware, it looks better than
before. (I also caught some bugs in the MRx register settings ...)		 dgisselq 2870d 18h /wbddr3/trunk/rtl/wbddrsdram.v
13 Cleanup, bug fixes--sadly, the code no longer works, so while it's "better"
in that it can build at 200MHz, it no longer works in the Verilator simulation.		 dgisselq 2871d 17h /wbddr3/trunk/rtl/wbddrsdram.v
12 Added the write-read and write-precharge extra delays into both module and
simulation.		 dgisselq 2872d 22h /wbddr3/trunk/rtl/wbddrsdram.v
11 Fixed the bugs Xilinx's tools pointed out. dgisselq 2872d 23h /wbddr3/trunk/rtl/wbddrsdram.v
10 This might just work ... at least, it passes my testbench. dgisselq 2873d 00h /wbddr3/trunk/rtl/wbddrsdram.v
9 Making progress: The singular write and pipe read tests work. Random pipe
reads still failing.		 dgisselq 2873d 00h /wbddr3/trunk/rtl/wbddrsdram.v
8 Singular reads and writes now work (in the Verilator simulator)--just not
pipelined reads or writes.		 dgisselq 2873d 09h /wbddr3/trunk/rtl/wbddrsdram.v
7 Make lots of progress. Reset works, and refresh is within a clock measurement
or two of working properly. Singular sequential writes work as well.		 dgisselq 2874d 18h /wbddr3/trunk/rtl/wbddrsdram.v
6 Lots of bug fixes. The controller now proceeds through the proper reset
logic into the first write. This includes activating the needed bank and the
next one, and then issuing the write command. It doesn't complete the write
command yet, but that's the next step.		 dgisselq 2875d 18h /wbddr3/trunk/rtl/wbddrsdram.v
5 Under Verilator/simulation testing, the core now properly brings the device
up from reset. Next step: opening/closing banks.		 dgisselq 2876d 00h /wbddr3/trunk/rtl/wbddrsdram.v
4 Work continues. A preliminary test-bench has been created. The core
has yet to pass through the reset cycle yet, so there's a lot of work
still to be done.		 dgisselq 2876d 16h /wbddr3/trunk/rtl/wbddrsdram.v
3 Fixes some, not all, of the Verilator build/lint errors. dgisselq 2877d 08h /wbddr3/trunk/rtl/wbddrsdram.v
2 Initial checkin. Pieces are not working yet, but the general approach is
starting to take shape.		 dgisselq 2877d 09h /wbddr3/trunk/rtl/wbddrsdram.v

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