URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [tbench/] [verilog/] [tb_xge_mac.sv] - Rev 21

Rev	Log message	Author	Age	Path
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4217d 21h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.sv
17	Fixed deprecated SystemC warnings	antanguay	4685d 21h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.sv
16	Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim	antanguay	4686d 03h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.sv
14	Change interface to big endian, added serdes examples to testbench	antanguay	5293d 22h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.v
12	Change interface to big endian, added serdes examples to testbench	antanguay	5293d 23h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.v
7	New directory structure.	root	5572d 08h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.v
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5848d 16h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.v
2	Initial revision	antanguay	5854d 20h	/xge_mac/trunk/tbench/verilog/tb_xge_mac.v