OpenCores
URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk] - Rev 29

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
29 All kinds of changes in different configurations. lcdsgmtr 3005d 12h /xucpu/trunk
28 Added project files for different systems. lcdsgmtr 3157d 14h /xucpu/trunk
27 When loading the 32k memory, do not let the process stop by a file that is
shorter, also make sure that the process is stopped if the file should be
longer.		 lcdsgmtr 3157d 14h /xucpu/trunk
26 Added test data for 32k memory.
Added GTKW configuration file.		 lcdsgmtr 3159d 12h /xucpu/trunk
25 Problem with memory: created conditional generate based upon data width
instead of address width.		 lcdsgmtr 3159d 12h /xucpu/trunk
24 Starting tracing through the component hierarchy initialisation. lcdsgmtr 3159d 12h /xucpu/trunk
23 Currently moved test bench to 10 bit address.
Created spreadsheet for filling memory with random data.
When testing, memory is apparently not initialised.		 lcdsgmtr 3159d 12h /xucpu/trunk
22 Update on makefile, because some parts are in other files. lcdsgmtr 3159d 12h /xucpu/trunk
21 Since all BRAM is unified in one component, this testbench is not necessary
anymore.		 lcdsgmtr 3159d 12h /xucpu/trunk
20 Update RAM package to allow for 15-bit address.
Update test bench to use address width parameter.		 lcdsgmtr 3159d 12h /xucpu/trunk
19 Makefile for building memory block testbench. lcdsgmtr 3159d 12h /xucpu/trunk
18 Ignore work files from GHDL. lcdsgmtr 3159d 12h /xucpu/trunk
17 Moving the generic block ram component piece by piece to a better
implementation.		 lcdsgmtr 3159d 12h /xucpu/trunk
16 Re-write of memory in function of initial array memory blocks. lcdsgmtr 3159d 12h /xucpu/trunk
15 Unification of all RAM parts into one interface. lcdsgmtr 3159d 12h /xucpu/trunk
14 Simple implementation project. lcdsgmtr 3291d 11h /xucpu/trunk
13 Updated smallest Xilinx configuration. lcdsgmtr 3291d 11h /xucpu/trunk
12 Update Xilinx configurations. lcdsgmtr 3291d 11h /xucpu/trunk
11 Successful run of the simulation. Correct results. lcdsgmtr 3291d 13h /xucpu/trunk
10 Correct build with GHDL. lcdsgmtr 3291d 13h /xucpu/trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.