OpenCores
URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk] - Rev 38

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
38 Building up the bare board with its components. lcdsgmtr 3012d 06h /xucpu/trunk
37 Write main board file as framework to follow. lcdsgmtr 3013d 09h /xucpu/trunk
36 Creating the new structure.
Adding entities and their architecture in separate directories.		 lcdsgmtr 3013d 09h /xucpu/trunk
35 Main work: create interface for instruction fetch, instruction cache,
instruction cache control and system bus.		 lcdsgmtr 3013d 09h /xucpu/trunk
34 Added makefile for this system.
Added board simulator file for this system.
Removed simple errors from main system.		 lcdsgmtr 3013d 09h /xucpu/trunk
33 Removal of simple compilation errors. lcdsgmtr 3013d 09h /xucpu/trunk
32 Added necessary red tape for implementing all these components. lcdsgmtr 3013d 09h /xucpu/trunk
31 Definition of system architecture library.
Definition of top level system architecture.
Main components used in top level system definition.		 lcdsgmtr 3013d 09h /xucpu/trunk
30 First implementation of cache memory. lcdsgmtr 3013d 09h /xucpu/trunk
29 All kinds of changes in different configurations. lcdsgmtr 3013d 09h /xucpu/trunk
28 Added project files for different systems. lcdsgmtr 3165d 10h /xucpu/trunk
27 When loading the 32k memory, do not let the process stop by a file that is
shorter, also make sure that the process is stopped if the file should be
longer.		 lcdsgmtr 3165d 10h /xucpu/trunk
26 Added test data for 32k memory.
Added GTKW configuration file.		 lcdsgmtr 3167d 09h /xucpu/trunk
25 Problem with memory: created conditional generate based upon data width
instead of address width.		 lcdsgmtr 3167d 09h /xucpu/trunk
24 Starting tracing through the component hierarchy initialisation. lcdsgmtr 3167d 09h /xucpu/trunk
23 Currently moved test bench to 10 bit address.
Created spreadsheet for filling memory with random data.
When testing, memory is apparently not initialised.		 lcdsgmtr 3167d 09h /xucpu/trunk
22 Update on makefile, because some parts are in other files. lcdsgmtr 3167d 09h /xucpu/trunk
21 Since all BRAM is unified in one component, this testbench is not necessary
anymore.		 lcdsgmtr 3167d 09h /xucpu/trunk
20 Update RAM package to allow for 15-bit address.
Update test bench to use address width parameter.		 lcdsgmtr 3167d 09h /xucpu/trunk
19 Makefile for building memory block testbench. lcdsgmtr 3167d 09h /xucpu/trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.