URL https://opencores.org/ocsvn/y80e/y80e/trunk

Subversion Repositories y80e

[/] [y80e/] [tags/] [plain-y80] - Rev 3

Rev	Log message	Author	Age	Path
3	Complete Y80 implementation. This version of CPU is described in book 'Microprocessor Design Using Verilog HDL' by Monte Dalryple from Systemyde. control.v file completed by me and author of CPU permits me to publish this project.	bsa	4030d 06h	/y80e/tags/plain-y80
2	Completed Y80 from Systemyde w/o anything else	bsa	4030d 06h	/y80e/trunk
1	The project and the structure was created	root	4030d 18h	/y80e/trunk