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Rev Log message Author Age Path
82 correct some typoes, thanks to Hu, Tao wsong0210 4019d 08h /
81 adding a solution in README to a cell lib problem. wsong0210 4387d 08h /
80 make the README file more understandable wsong0210 4467d 04h /
79 update comments in sim compile.sh to clarify that synthesis must be done before post-synthesis simulation wsong0210 4527d 14h /
78 pass link wsong0210 4694d 01h /
77 pass syn elaboration wsong0210 4695d 01h /
76 fix syntex wsong0210 4699d 01h /
75 code finished, start the debugging wsong0210 4699d 02h /
74 in/out buffer finished wsong0210 4700d 02h /
73 input buffer wsong0210 4707d 01h /
72 clos-opt ongoing, Clos switch finished, nxt input buffer wsong0210 4708d 01h /
71 the buffered 2-stage Clos switch wsong0210 4709d 01h /
70 clos-opt ongoing wsong0210 4709d 01h /
69 central module of the Clos wsong0210 4712d 01h /
68 rewite the clos switch in the SDM-Clos-buf router wsong0210 4713d 01h /
67 structure not good, prepare to use new files wsong0210 4713d 03h /
66 clos opt ongoing wsong0210 4727d 19h /
65 pipeline controller wsong0210 4727d 20h /
64 clos opt ongoing wsong0210 4727d 20h /
63 clos opt ongoing wsong0210 4728d 00h /

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