URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] - Rev 10

Rev	Log message	Author	Age	Path
10	Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure.	ash_riple	4463d 21h	/
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4464d 16h	/
8	Added fault handling of wrong input length in the GUI.	ash_riple	4468d 16h	/
7	Added references related to "Bus Monitor".	ash_riple	4468d 20h	/
6	Updated to 2.1. New features added as in doc/Revision History.txt.	ash_riple	4469d 16h	/
5	Created code base for 2.x development. Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.	ash_riple	4472d 17h	/
4	Created tag for original source code. Version 1.0.	ash_riple	4472d 19h	/
3	Added original article.	ash_riple	4472d 19h	/
2	Checked in working code base.	ash_riple	4476d 16h	/
1	The project and the structure was created	root	4477d 06h	/