URL https://opencores.org/ocsvn/csa/csa/trunk

Subversion Repositories csa

[/] - Rev 39

Rev	Log message	Author	Age	Path
39	add usb controler module	simon111	5533d 01h	/
38	improve the ledseg control module the register h must be 2bits width	simon111	5533d 19h	/
37	improve write_data systemcall,	simon111	5534d 00h	/
36	improve read_date vpi sytemcall, add offset and size argument	simon111	5534d 02h	/
35	csa cli support binary test data	simon111	5534d 06h	/
34	add binary test date (only sw_sim now )	simon111	5534d 09h	/
33	improve ledseg controler module	simon111	5534d 20h	/
32	fix a compile error	simon111	5534d 20h	/
31	remove pc execute file	simon111	5534d 21h	/
30	begin vailating on fpga	simon111	5534d 21h	/
29	fix some bugs	simon111	5535d 21h	/
28	create a quartus10 project for test the core	simon111	5535d 21h	/
27	improve makefiles	simon111	5536d 08h	/
26	Added old uploaded documents to new repository.	root	5571d 21h	/
25	Added old uploaded documents to new repository.	root	5572d 14h	/
24	New directory structure.	root	5572d 14h	/
23	testing key_schedule module	simon111	5655d 21h	/
22	decrypt module testbench update	simon111	5695d 20h	/
21	decrypt module passed basicly, it's not good code type	simon111	5695d 20h	/
20	finished the stream_cypher module, this module passed modelsim , but doesn't pass veriwell, i don't know why	simon111	5709d 19h	/