URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] - Rev 67

Rev	Log message	Author	Age	Path
67	modify mgmt_miim_rdy timing sequence	fisher5090	6567d 05h	/
66	comments added	fisher5090	6567d 09h	/
65	bad coding style, but works, will be modified later	fisher5090	6567d 12h	/
64	no message	fisher5090	6569d 22h	/
63	remove pad function added, using xilinx vp20 -6 as target FPGA, passes post place and route simulation	fisher5090	6569d 22h	/
62	no message	fisher5090	6570d 05h	/
61	no message	fisher5090	6570d 07h	/
60	change rxd_in, rxc_in and rxclk_in signals'name to xgmii_rxd, xgmii_rxc and xgmii_rxclk	fisher5090	6570d 07h	/
59	first version	fisher5090	6570d 08h	/
58	configuration vector select inband fcs or not	fisher5090	6570d 13h	/
57	both inband fcs and no inband fcs are OK	fisher5090	6570d 13h	/
56	no message	fisher5090	6571d 05h	/
55	testbench for normal frame and error frame	fisher5090	6571d 05h	/
54	removed	fisher5090	6571d 05h	/
53	testbench for normal and error frame	fisher5090	6571d 09h	/
52	modified the rx_good_frame and rx_bad_frame timing sequence	fisher5090	6571d 09h	/
51	modified	fisher5090	6573d 13h	/
50	good version	fisher5090	6573d 13h	/
49	datasheet for receive module	fisher5090	6573d 13h	/
48	no message	fisher5090	6574d 05h	/