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Rev Log message Author Age Path
73 Corrected AXI4 wrapper timing bug.
Added system-level instantiation examples for XPS and Qsys.		 ash_riple 3660d 00h /
72 Minor changes. ash_riple 3985d 20h /
71 Added architecture description in the doc folder. ash_riple 3985d 22h /
70 Updated Altera Qsys instantiation script. ash_riple 4141d 19h /
69 Fixed the negative period adjustment bug. ash_riple 4143d 00h /
68 Refined the vendor specific IP instanttiation. Now DCFIFO is instantiated as a vendor specific IP in PAR directory. ash_riple 4143d 03h /
67 Updated the WishBone IP top and Qsys IP top. ash_riple 4144d 20h /
66 Added IP instantiation support for: QSys, XPS and WishBone. ash_riple 4145d 20h /
65 Added WishBone compatible wrapper for register access. ash_riple 4150d 00h /
64 Added PTPv2 timing analyzer tool. ash_riple 4151d 21h /
63 Updated the simulation script under Linux. ash_riple 4155d 01h /
62 Removed environment variable settings in the simulation script under Windows. ash_riple 4155d 01h /
61 Made different scripts for top-level simulation to run under Linux. ash_riple 4155d 02h /
60 Made different scripts for top-level simulation to run under Linux. ash_riple 4155d 02h /
59 Made different scripts for top-level simulation to run under Windows. ash_riple 4155d 02h /
58 Added output rtc_time_one_pps for clock accuracy measurement. 1PPS output is leading edge aligned with the PTP time output on boundary of 1s. edn_walter 4427d 23h /
57 Added parameters of frame header constants for packet parsing. edn_walter 4428d 01h /
56 Added parameter of VLAN TPID for stacked VLAN parsing. edn_walter 4428d 01h /
55 Updated the SOPC Builder example with GMII/MII support. edn_walter 4428d 22h /
54 Added support for MII interface as well as GMII interface. Updated unit and top-level test cases. edn_walter 4428d 22h /

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