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Rev Log message Author Age Path
347 Xilinx ISE Project file rhoads 5584d 11h /
346 Support optional 4KB cache rhoads 5621d 11h /
345 Commented out optional mult speedup rhoads 5625d 08h /
344 Fixed compiler warning rhoads 5625d 08h /
343 Initial working cache rhoads 5625d 08h /
342 Changed simple cache rhoads 5625d 08h /
341 Permit large file transfers when running on windows rhoads 5625d 08h /
340 Get the length of a file rhoads 5625d 08h /
339 Format output of ls rhoads 5625d 08h /
338 Fix filename problem with 9th file in directory rhoads 5625d 08h /
337 Initial attempt at a cache rhoads 5630d 12h /
336 Better support Linux rhoads 5663d 05h /
335 Use enable signal for byte_we rhoads 5672d 06h /
334 Short time for averaging read signal for 12.5 MHz case rhoads 5682d 06h /
333 Updated Altera lpm_ram_dp usage for Cyclone FPGAs rhoads 5682d 06h /
332 Updated Altera lpm_ram_dp rhoads 5682d 06h /
331 Commented out unconnected signals rhoads 5743d 06h /
330 Simplify sscanf() rhoads 5752d 17h /
329 Fix interrupt line comment rhoads 5834d 05h /
328 sprintf() will add '\r' before '\n' rhoads 5846d 18h /

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