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Rev Log message Author Age Path
63 Upgrade makefiles for use with the upgraded toolchain skordal 3192d 00h /
62 Add a couple of missing signals to a sensitivity list skordal 3220d 01h /
61 Add 7-segment display controller to the Potato SoC skordal 3221d 04h /
60 Remove out-of-date comment skordal 3234d 20h /
59 Remove branch: "new-privileged-isa" skordal 3254d 21h /
58 Merge branch new-privileged-isa (r48-r57) into trunk

This adds support for the newly published supervisor extensions
version 1.7. In addition, a processor datasheet has been added
and the timer_clk signal has been properly connected in the
example design and the SoC testbench.		 skordal 3255d 00h /
57 Add processor datasheet skordal 3255d 01h /
56 Remove old and outdated processor manual skordal 3255d 01h /
55 Use timer_clk for the example design and SoC testbench skordal 3255d 02h /
54 Update benchmarks to work with supervisor spec v1.7 skordal 3259d 17h /
53 Upgrade processor core to conform to the supervisor spec v1.7 skordal 3261d 18h /
52 Correct .data section of sw-jal test skordal 3261d 18h /
51 Add scall/ecall, sbreak/ebreak and timer interrupt tests skordal 3261d 18h /
50 Update test environment to the new supervisor ISA skordal 3273d 18h /
49 Correct spelling of "privileged" skordal 3283d 17h /
48 Create branch for upgrading to the new privileged ISA skordal 3283d 17h /
47 Tag version 0.1 of the Potato Processor skordal 3284d 01h /
46 Remove branch: cache-playground skordal 3286d 19h /
45 Merge branch cache-playground (r23-r30 and r34-r44) into trunk

This primarily adds the following features the the processor:
- A direct-mapped instruction cache with configurable cache line width and
number of cache lines.
- Various bug fixes for bugs that appeared when the processor could run
instructions at full speed but had to stall for data.
- A "Hello World" test application.		 skordal 3286d 19h /
44 Add instruction cache and use the WB adapter as dmem interface skordal 3286d 20h /

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