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13 - To simplify the exception traitement: Instruction are executed serialy.
- Exception event must be treated CONCURRENTLY with the other event that stall the pipeline.
ameziti 5965d 13h /
12 To simplify the exception traitement: Instruction are executed serialy. ameziti 5965d 14h /
11 Exception event must be treated CONCURRENTLY with the other event that stall the pipeline. ameziti 5965d 14h /
10 Modification of the CP0. ameziti 5965d 14h /
9 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.
ameziti 5965d 14h /
8 Enhancement of the "Controler specification doc". ameziti 5968d 14h /
7 Add Pipeline Controler specification documentation. ameziti 5969d 13h /
6 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.
ameziti 5969d 15h /
5 Remove the Multiple Arithmetic Unit fonction.
- The Pipeline must stall when Mult/Div unit is busy.
- Whether there's a mflo or mfhi.
- see `define MULTIPLE_ALU
ameziti 5970d 12h /
4 Add Soc Image in the Specification documentation ameziti 5991d 15h /
3 This commit was manufactured by cvs2svn to create tag 'arelease'. 5992d 23h /
2 First Import the project on the opencores.org CVS server ameziti 5992d 23h /
1 Standard project directories initialized by cvs2svn. 5992d 23h /

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