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Subversion Repositories r2000

[/] - Rev 23

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Rev	Log message	Author	Age	Path
23	- when freeze or stall; don't let memory operations - Modification on the CP0 - The CP0 is deplaced in the WB stage - The INT, SI event signals are treated asynchronously in the WB stage - The rCAUSE register is asynchronous now - The wException signal is asyncronous instantanously - Add a repeat/continous treatement (not completed yet) - *** The "INT EXCEPTION NO STALL" work correctly	ameziti	5929d 19h	/
22	- Some modifications for testing exception.	ameziti	5964d 11h	/
21	- Flush must be on all signals in the pipeline.	ameziti	5964d 11h	/
20	- Modification of CP0 to wait the end of all stalls before to process Exception. - Set "Exception sign" active until all Stalls are completed.	ameziti	5964d 19h	/
19	- Exception signals must be stalled, flushed, stoped or cleared(except reset) - Look at 14-07-2007 - except the asynchronous event like "external interruption"	ameziti	5965d 01h	/
18	- Read/Write of the CP0 register is in the WB stage, but Exception detection begin from the MEM stage.	ameziti	5965d 01h	/
17	- UnFonctional Modifications: Change the name of the address port of "CP0".	ameziti	5965d 01h	/
16	- Remove All generable files from the project.	ameziti	5965d 09h	/
15	- UnFonctional Modifications. - Change the "CP0" define to "EXCEPTION".	ameziti	5965d 10h	/
14	Remove unnecessary files from project.	ameziti	5965d 18h	/
13	- To simplify the exception traitement: Instruction are executed serialy. - Exception event must be treated CONCURRENTLY with the other event that stall the pipeline.	ameziti	5965d 18h	/
12	To simplify the exception traitement: Instruction are executed serialy.	ameziti	5965d 19h	/
11	Exception event must be treated CONCURRENTLY with the other event that stall the pipeline.	ameziti	5965d 19h	/
10	Modification of the CP0.	ameziti	5965d 20h	/
9	When D-Cache miss, there's no need to stall MEMWB and freeze WB. The solution is to flush MEMWB only.	ameziti	5965d 20h	/
8	Enhancement of the "Controler specification doc".	ameziti	5968d 20h	/
7	Add Pipeline Controler specification documentation.	ameziti	5969d 18h	/
6	When D-Cache miss, there's no need to stall MEMWB and freeze WB. The solution is to flush MEMWB only.	ameziti	5969d 20h	/
5	Remove the Multiple Arithmetic Unit fonction. - The Pipeline must stall when Mult/Div unit is busy. - Whether there's a mflo or mfhi. - see `define MULTIPLE_ALU	ameziti	5970d 18h	/
4	Add Soc Image in the Specification documentation	ameziti	5991d 20h	/

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Subversion Repositories r2000

[/] - Rev 23

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