OpenCores
URL https://opencores.org/ocsvn/rs232_interface/rs232_interface/trunk

Subversion Repositories rs232_interface

[/] - Rev 18

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
18 Added RX state verification for start bit process.
Added loop in the parallel interface of TB.		 akram.mashni 4341d 13h /
17 First commit of uart test bench.
WARNING: Not yet finished! Commited for back up.		 akram.mashni 4773d 21h /
16 Project's block diagram.
It will be use in the datasheet.
(Compression level 5 when export from .odg file).		 akram.mashni 4875d 06h /
15 Removed uncompressed image with big size. akram.mashni 4875d 06h /
14 Block diagram image of 2011-01-16 version.
It will be use in the datasheet.
(Compression level 5 when export from .odg file).		 akram.mashni 4875d 06h /
13 Initial commit of documentation.
Created block diagram (OpenOffice Draw format).		 akram.mashni 4875d 06h /
12 Updated news of uart.vhd commit. akram.mashni 4876d 09h /
11 Moved debouncer to a new process.
Fixed rx_clk_en generation.
Fixed start of reception condition on rx FSM.		 akram.mashni 4876d 09h /
10 Implemented asynchronous mode and RX clock regeneration.
NOT TESTED !!!		 akram.mashni 4884d 03h /
9 Updated change log. akram.mashni 4921d 18h /
8 Added Recommended Tools akram.mashni 4921d 18h /
7 Implemented PARITY (not tested!). akram.mashni 4923d 05h /
6 Fixed/improved header.
Changed SPACEs to TABs.		 akram.mashni 4924d 10h /
5 Added comments to port map. akram.mashni 4931d 15h /
4 Added "Change Log".
Added "About"		 akram.mashni 4931d 16h /
3 Added main file.
Fisrt commit.
Tested in the following conditions:
- Baud rate: 9600 bps.
- Implementation: Xilinx Spartan3e500 (Nexys2 Kit - Digilent)
- Main clock 50 MHz		 akram.mashni 4931d 16h /
2 Initial Commit luciorp 4988d 04h /
1 The project and the structure was created root 5016d 01h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.