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14 Added VHDL source code and document for VHDL version. jclaytons 2426d 23h /
13 Improved the Documentation jclaytons 3933d 03h /
12 bugfix: data write transfer bugfix

msb of data word (4-byte word) was transmitted wrongly

Signed-off-by: Marek Czerski <ma.czerski@gmail.com>		 rozpruwacz 3937d 22h /
11 doccumentation update

block count register clarification

Signed-off-by: Marek Czerski <ma.czerski@gmail.com>		 rozpruwacz 3938d 13h /
10 README update: TODO list added

Signed-off-by: Marek Czerski <ma.czerski@gmail.com>		 rozpruwacz 3938d 13h /
9 README update: reference to linux driver

Signed-off-by: Marek Czerski <ma.czerski@gmail.com>		 rozpruwacz 3938d 13h /
8 updated header files with project address from OpenCores

Signed-off-by: Marek Czerski <ma.czerski@gmail.com>		 rozpruwacz 3941d 04h /
7 README update: reference to example project added

Signed-off-by: Marek Czerski <ma.czerski@gmail.com>		 rozpruwacz 3941d 04h /
6 voltage register definition change

voltage register now contains the value of the supply voltage
expressed in mV.

Signed-off-by: Marek Czerski <ma.czerski@gmail.com>		 rozpruwacz 3941d 09h /
5 readme update again

Signed-off-by: Marek Czerski <ma.czerski@gmail.com>		 rozpruwacz 3941d 09h /
4 updated readme

Signed-off-by: Marek Czerski <ma.czerski@gmail.com>		 rozpruwacz 3941d 09h /
3 initial commit of the project

first usable version of the WISHBONE SD Card Controller IP Core

Signed-off-by: Marek Czerski <ma.czerski@gmail.com>		 rozpruwacz 3941d 09h /
2 first commit rozpruwacz 3941d 09h /
1 The project and the structure was created root 3942d 00h /

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