OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] - Rev 169

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
169 +sdc file for timing analysis rkastl 4897d 13h /
168 TbdSd synthesis script reaches timing constraints. rkastl 4897d 13h /
167 Read+Modify+Write works on HW

+ Fixed CRC status token (not mentioned in simplified spec)
+ Improved TestWbMaster to RMW		 rkastl 4897d 13h /
166 tbTbdSd: fixed rkastl 4897d 13h /
165 Only use synchronous high active reset in SDHC-SC-Core. rkastl 4897d 13h /
164 Headers updated (LGPL, consistent format) rkastl 4897d 13h /
163 Header-Skript supports writing to file and infile replacement. rkastl 4897d 13h /
162 Script for generating headers created. rkastl 4897d 13h /
161 Verification:
CardModel: Check CRC on received data		 rkastl 4897d 13h /
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4897d 13h /
159 Verification:
Further work: Checking RAM Actions and reading data is still
missing		 rkastl 4897d 13h /
158 Verification:
Work on Checking
Functional coverage		 rkastl 4897d 13h /
157 Verification:
Testcase with Reads works but Verification not completly
implemented.		 rkastl 4897d 13h /
156 SdVerification:
+ Split a SdCoreTransaction into multiple WbTransactions: Proof
of Concept with a ReadSingleBlock-Transaction
+ Finish after certain amount of time and present simulation
result		 rkastl 4897d 13h /
155 SdVerification:
continue to work on it, not done.		 rkastl 4897d 13h /
154 SdVerification:
- started sending with mailboxes		 rkastl 4897d 13h /
153 SdVerification:
further development, not done by far		 rkastl 4897d 13h /
152 SdClockMaster:
Generate InStrobe so that it the sd bus gets captured on the
rising edge of the clock in high speed mode		 rkastl 4897d 13h /
151 Verification:
+ redesign: not functional yet		 rkastl 4897d 13h /
150 Testbed:
+ Simulation made possible
+ Write works
- Sometimes the alignment in the block is not right		 rkastl 4897d 13h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.